View IMSH1GU13A1F1C-10F_3771190.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

imsh51u03a1f1c imsh51e03a1f1c imsh1gu13a1f1c imsh1ge13a1f1c 240-pin ddr3 unbuffered memory modules 512 mb, 1gb rohs compliant advance internet data sheet rev. 0.54 november 2007
advance internet data sheet imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm qag_techdoc_rev411 / 3.31 qag / 2007-01-22 2 11202007-pqti-i4uf we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com imsh51u03a1f1c, imsh51e03a1f1c, imsh1gu13a1f1c revision history: 2007-11, rev. 0.54 page subjects (major chan ges since last revision) all editorial changes. previous revision: rev. 0.53, 2007-11
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 3 11202007-pqti-i4uf 1overview this chapter gives an overview of the 240?pin unbuffered ddr3 dual-in-line memory modules product family and describes its main characteristics. 1.1 features ? 240-pin 8-byte ddr3 sdram unbuffered dual-in-line memory modules . ? module organization: 128m 64, 128m 72, 64m 64, 64m 72 chip organization: 64m 8. ? pc3-12800, pc3-10600, pc3-8500 and pc3-6400 module speed grades. ? 1gb, 512mb modules built with 512mb ddr3 sdrams in packages pg-tfbga-78 ? ddr3 sdrams with a single 1.5 v ( 0.075 v) power supply. ? asynchronous reset. ? programmable cas latency, cas write latency, additive latency, burst length and burst type. ? on-die-termination (odt) and dynamic odt for improved signal integrity. ? refresh. self refresh and power down modes. ? zq calibration for output driver and odt. ? system level timing calibration support via write leveling and multi purpose register (mpr) read pattern. ? serial presence detect with eeprom. ? udimm dimensions: 133.35 mm x 30 mm. ? based on standard reference raw cards: 'a', 'b', 'd' and 'e' ? rohs compliant products 1) . table 1 performance table for ddr3?1600 and ddr3?1333 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. qimonda speed code ?16h ?16j ?13g ?13h ?13j unit note 1) 1) the available cl and cwl settings depend on t he sdram device speed bin. the cl setting and cwl setting result in maximum but also minimum clock frequency re quirements. when making a selecti on of operating clock frequency, bot h need to be fulfilled: requirem ents from cl setting as well as requirements from cwl setting. for details, refer to chapter 4.1 speed bins. module speed bin pc3 ?12800h ?12800j ?10600g ?10600h ?10600j device speed bin ddr3 ?1600h ?1600j ?1333g ?1333h ?1333j cl- n rcd - n rp 9-9-9 10-10-10 8-8-8 9-9-9 10-10-10 cl and cwl settings for maximum clock frequency cl = 9 cwl = 8 cl = 10 cwl = 8 cl = 8 cwl = 7 cl = 9 cwl = 7 cl = 10 cwl = 7 mhz maximum clock frequency and data rate with above cl and cwl settings 800 1600 800 1600 667 1333 667 1333 667 1333 mhz mb/s minimum clock frequency and data rate with above cl and cwl settings 667 1333 667 1333 533 1066 533 1066 533 1066 mhz mb/s
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 4 11202007-pqti-i4uf table 2 performance table for ddr3?1066 and ddr3?800 qimonda speed code ?10e ?10f ?10g ?08d ?08e unit note 1) 1) the available cl and cwl settings depend on t he sdram device speed bin. the cl setting and cwl setting result in maximum but also minimum clock frequency re quirements. when making a selecti on of operating clock frequency, bot h need to be fulfilled: requirem ents from cl setting as well as requirements from cwl setting. for details, refer to chapter 4.1 speed bins. module speed bin pc3 ?8500e ?8500f ?8500g ?6400d ?6400e device speed bin ddr3 ?1066e ?1066f ?1066g ?800d ?800e cl- n rcd - n rp 6-6-6 7-7-7 8-8-8 5-5-5 6-6-6 cl and cwl settings for maximum clock frequency cl = 6 cwl = 6 cl = 7 cwl = 6 cl = 8 cwl = 6 cl = 5 cwl = 5 cl = 6 cwl = 5 mhz maximum clock frequency and data rate with above cl and cwl settings 533 1066 533 1066 533 1066 400 800 400 800 mhz mb/s minimum clock frequency and data rate with above cl and cwl settings 400 800 400 800 400 800 300 600 300 600 mhz mb/s
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 5 11202007-pqti-i4uf 1.2 description the qimonda imsh[51/1g][u/e]xxa1f1c are unbuffered dimm (udimm) family with 30 mm height based on ddr3 sdram technology. dimms are available non-ecc modules in128m 64 (1gb), 64m 64 (512mb) and as ecc modules in 128m 72 (1gb), 64m 72 (512mb) organization and density, intended for mounting into 240 pin connector sockets. the memory array is designed with 512mb double data rate (ddr3) synchronous drams. de-coupling capacitors, stub resistors, calibration resistor s and termination resistors are mounted on the pcb board. the dimms feature serial presence detect based on a 2 56 byte serial eeprom device using the 2-pin i2c protocol. the first 176 bytes are programmed with module specific spd data. table 3 ordering information table qimonda part number compliance code description 512 mbyte non-ecc unbuffered dimm imsh51u03a1f1c imsh51u03a1f1c?08d 512mb 1r8 pc3?6400u?5-xx?a0 240-pin 512 mbyte ddr3 unbuffered dimm with one rank for non-ecc applications. the memory rank consists of eight ddr3 components in x8 organization. standard reference card a is used on this assembly. used ddr3 sdram component part number: idsh51-03a1f1c density: 512 mbit organization: 64mbit 8 address bits (row/column/bank): 13/10/3 imsh51u03a1f1c?08e 512mb 1r8 pc3?6400u?6-xx?a0 imsh51u03a1f1c?10e 512mb 1r8 pc3?8500u?6-xx?a0 imsh51u03a1f1c?10f 512mb 1r8 pc3?8500u?7-xx?a0 imsh51u03a1f1c?10g 512mb 1r8 pc3?8500u?8-xx?a0 imsh51u03a1f1c?13g 512mb 1r8 pc3?10600u?8-xx?a0 imsh51u03a1f1c?13h 512mb 1r8 pc3?10600u?9-xx?a0 imsh51u03a1f1c?13j 512mb 1r8 pc3?10600u?10-xx?a0 imsh51u03a1f1c?16h 512mb 1r8 pc3?12800u?9-xx?a0 imsh51u03a1f1c?16j 512mb 1r8 pc3?12800u?10-xx?a0 512 mbyte ecc unbuffered dimm imsh51e03a1f1c imsh51e03a1f1c?08d 512mb 1r8 pc3?6400e?5-xx?d0 240-pin 512 mbyte ddr3 unbuffered dimm with one rank for ecc applications. the memory rank consists of nine ddr3 components in x8 organization. standard reference card d is used on this assembly. used ddr3 sdram component part number: idsh51-03a1f1c density: 512 mbit organization: 64mbit 8 address bits (row/column/bank): 13/10/3 imsh51e03a1f1c?08e 512mb 1r8 pc3?6400e?6-xx?d0 imsh51e03a1f1c?10e 512mb 1r8 pc3?8500e?6-xx?d0 imsh51e03a1f1c?10f 512mb 1r8 pc3?8500e?7-xx?d0 imsh51e03a1f1c?10g 512mb 1r8 pc3?8500e?8-xx?d0 imsh51e03a1f1c?13g 512mb 1r8 pc3?10600e?8-xx?d0 imsh51e03a1f1c?13h 512mb 1r8 pc3?10600e?9-xx?d0 imsh51e03a1f1c?13j 512mb 1r8 pc3?10600e?10-xx?d0 imsh51e03a1f1c?16h 512mb 1r8 pc3?12800e?9-xx?d0 imsh51e03a1f1c?16j 512mb 1r8 pc3?12800e?10-xx?d0
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 6 11202007-pqti-i4uf 1024 mbyte non-ecc unbuffered dimm imsh1gu13a1f1c imsh1gu13a1f1c?08d 1gb 2r8 pc3?6400u?5-xx?b0 240-pin 1024 mbyte ddr3 unbuffered dimm with two ranks for non-ecc applications. each memory rank consists of eight ddr3 components in x8 organization. standard reference card b is used on this assembly. used ddr3 sdram component part number: idsh51-03a1f1c density: 512 mbit organization: 64mbit 8 address bits (row/column/bank): 13/10/3 imsh1gu13a1f1c?08e 1gb 2r8 pc3?6400u?6-xx?b0 imsh1gu13a1f1c?10e 1gb 2r8 pc3?8500u?6-xx?b0 imsh1gu13a1f1c?10f 1gb 2r8 pc3?8500u?7-xx?b0 imsh1gu13a1f1c?10g 1gb 2r8 pc3?8500u?8-xx?b0 imsh1gu13a1f1c?13g 1gb 2r8 pc3?10600u?8-xx?b0 imsh1gu13a1f1c?13h 1gb 2r8 pc3?10600u?9-xx?b0 imsh1gu13a1f1c?13j 1gb 2r8 pc3?10600u?10-xx?b0 imsh1gu13a1f1c?16h 1gb 2r8 pc3?12800u?9-xx?b0 imsh1gu13a1f1c?16j 1gb 2r8 pc3?12800u?10-xx?b0 1024 mbyte ecc unbuffered dimm imsh1ge13a1f1c imsh1ge13a1f1c?08d 1gb 2r8 pc3?6400e?5-xx?e0 2 40-pin 1024 mbyte ddr3 unbuffered dimm with two ranks for ecc applications. each memory rank consists of nine ddr3 components in x8 organization. standard reference card e is used on this assembly. used ddr3 sdram component part number: idsh51-03a1f1c density: 512 mbit organization: 64mbit 8 address bits (row/column/bank): 13/10/3 imsh1ge13a1f1c?08e 1gb 2r8 pc3?6400e?6-xx?e0 imsh1ge13a1f1c?10e 1gb 2r8 pc3?8500e?6-xx?e0 imsh1ge13a1f1c?10f 1gb 2r8 pc3?8500e?7-xx?e0 imsh1ge13a1f1c?10g 1gb 2r8 pc3?8500e?8-xx?e0 imsh1ge13a1f1c?13g 1gb 2r8 pc3?10600e?8-xx?e0 imsh1ge13a1f1c?13h 1gb 2r8 pc3?10600e?9-xx?e0 imsh1ge13a1f1c?13j 1gb 2r8 pc3?10600e?10-xx?e0 imsh1ge13a1f1c?16h 1gb 2r8 pc3?12800e?9-xx?e0 imsh1ge13a1f1c?16j 1gb 2r8 pc3?12800e?10-xx?e0 qimonda part number compliance code description
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 7 11202007-pqti-i4uf 2 configuration 2.1 pin configuration table 4 pin configuration of ddr3 udimm - 240 pins pin name eda signal name 1) pin no. pin type buffer type function clock signals ck0 ck0_t 184 i sstl differnetial clock inputs [1:0] ck0 ck0_c 185 i sstl ck1 ck1_t 63 i sstl ck1 ck1_c 64 i sstl control signals cke0 cke0 50 i sstl clock enable [1:0] cke1/nc cke1 169 i sstl odt0 odt0 195 i sstl on-die termination [1:0] odt1/nc odt1 77 i s0 s0_n 193 i sstl chip select [2:0] s1 /nc s1_n 76 i sstl command signals ras ras_n 192 i sstl row address strobe cas cas_n 74 i sstl column address strobe we we_n 73 i sstl write enable bank address signals ba0 ba0 71 i sstl bank address bus[2:0] ba1 ba1 190 i sstl ba2 ba2 52 i sstl address signals a0 a0 188 i sstl address bus [15:0] a1 a1 181 i sstl a2 a2 61 i sstl a3 a3 180 i sstl a4 a4 59 i sstl a5 a5 58 i sstl
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 8 11202007-pqti-i4uf a6 a6 178 i sstl address bus [15:0] a7 a7 56 i sstl a8 a8 177 i sstl a9 a9 175 i sstl a10/ap a10 70 i sstl a11 a11 55 i sstl a12/bc a12 174 i sstl a13 a13 196 i sstl a14 a14 172 i sstl a15/nc a15 171 i sstl data signals dq0 dq0 3 i/o sstl data bus [63:0] dq1 dq1 4 i/o sstl dq2 dq2 9 i/o sstl dq3 dq3 10 i/o sstl dq4 dq4 122 i/o sstl dq5 dq5 123 i/o sstl dq6 dq6 128 i/o sstl dq7 dq7 129 i/o sstl dq8 dq8 12 i/o sstl dq9 dq9 13 i/o sstl dq10 dq10 18 i/o sstl dq11 dq11 19 i/o sstl dq12 dq12 131 i/o sstl dq13 dq13 132 i/o sstl dq14 dq14 137 i/o sstl dq15 dq15 138 i/o sstl dq16 dq16 21 i/o sstl dq17 dq17 22 i/o sstl dq18 dq18 27 i/o sstl dq19 dq19 28 i/o sstl dq20 dq20 140 i/o sstl dq21 dq21 141 i/o sstl dq22 dq22 146 i/o sstl dq23 dq23 147 i/o sstl dq24 dq24 30 i/o sstl dq25 dq25 31 i/o sstl dq26 dq26 36 i/o sstl dq27 dq27 37 i/o sstl pin name eda signal name 1) pin no. pin type buffer type function
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 9 11202007-pqti-i4uf dq28 dq28 149 i/o sstl data bus [63:0] dq29 dq29 150 i/o sstl dq30 dq30 155 i/o sstl dq31 dq31 156 i/o sstl dq32 dq32 81 i/o sstl dq33 dq33 82 i/o sstl dq34 dq34 87 i/o sstl dq35 dq35 88 i/o sstl dq36 dq36 200 i/o sstl dq37 dq37 201 i/o sstl dq38 dq38 206 i/o sstl dq39 dq39 207 i/o sstl dq40 dq40 90 i/o sstl dq41 dq41 91 i/o sstl dq42 dq42 96 i/o sstl dq43 dq43 97 i/o sstl dq44 dq44 209 i/o sstl dq45 dq45 210 i/o sstl dq46 dq46 215 i/o sstl dq47 dq47 216 i/o sstl dq48 dq48 99 i/o sstl dq49 dq49 100 i/o sstl dq50 dq50 105 i/o sstl dq51 dq51 106 i/o sstl dq52 dq52 218 i/o sstl dq53 dq53 219 i/o sstl dq54 dq54 224 i/o sstl dq55 dq55 225 i/o sstl dq56 dq56 108 i/o sstl dq57 dq57 109 i/o sstl dq58 dq58 114 i/o sstl dq59 dq59 115 i/o sstl dq60 dq60 227 i/o sstl dq61 dq61 228 i/o sstl dq62 dq62 233 i/o sstl dq63 dq63 234 i/o sstl pin name eda signal name 1) pin no. pin type buffer type function
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 10 11202007-pqti-i4uf cb0/nc cb0 39 i/o sstl check bit [7:0] cb1/nc cb1 40 i/o sstl cb2/nc cb2 45 i/o sstl cb3/nc cb3 46 i/o sstl cb4/nc cb4 158 i/o sstl cb5/nc cb5 159 i/o sstl cb6/nc cb6 164 i/o sstl cb7/nc cb7 165 i/o sstl dqs0 dqs0_t 7 i/o sstl data strobe signals [8:0] dqs0 dqs0_c 6 i/o sstl dqs1 dqs1_t 16 i/o sstl dqs1 dqs1_c 15 i/o sstl dqs2 dqs2_t 25 i/o sstl dqs2 dqs2_c 24 i/o sstl dqs3 dqs3_t 34 i/o sstl dqs3 dqs3_c 33 i/o sstl dqs4 dqs4_t 85 i/o sstl dqs4 dqs4_c 84 i/o sstl dqs5 dqs5_t 94 i/o sstl dqs5 dqs5_c 93 i/o sstl dqs6 dqs6_t 103 i/o sstl dqs6 dqs6_c 102 i/o sstl dqs7 dqs7_t 112 i/o sstl dqs7 dqs7_c 111 i/o sstl dqs8/nc dqs8_t 43 i/o sstl dqs8 /nc dqs8_c 42 i/o sstl dm0 dm0 125 i sstl data mask signals [8:0] dm1 dm1 134 i sstl dm2 dm2 143 i sstl dm3 dm3 152 i sstl dm4 dm4 203 i sstl dm5 dm5 212 i sstl dm6 dm6 221 i sstl dm7 dm7 230 i sstl dm8/nc dm8 161 i sstl eeprom scl scl 118 i cmos serial bus clock sda sda 238 i/o od serial data bus pin name eda signal name 1) pin no. pin type buffer type function
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 11 11202007-pqti-i4uf sa0 sa0 117 i cmos serial address select bus [2:0] sa1 sa1 237 i cmos sa2 sa2 119 i cmos power supply v dd vdd 51, 54, 57, 60, 62, 65, 66, 69, 72, 75, 78, 170, 173, 176, 179, 182, 183, 186, 189, 191, 194, 197, pwr - power supply v ss vss 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 80, 83, 86, 89,92, 95, 98, 101, 104, 107, 110, 113, 116, 121, 124, 127, 130, 133, 136, 139, 142, 145, 148, 151, 154, 157, 160, 163, 166, 199, 202, 205, 208, 211, 214, 217, 220, 223, 226, 229, 232, 235, 239 gnd - ground v ref.dq vrefdq 1 ai - reference voltage v ref.ca vrefca 67 ai - reference voltage v tt vtt 120 , 240 pwr - termination voltage v ddspd vddspd 236 - eeprom power supply other pins pin name eda signal name 1) pin no. pin type buffer type function
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 12 11202007-pqti-i4uf table 5 abbreviations for pin type table 6 abbreviations for buffer type reset reset_n 168 i cmos asynchronous reset nc nc 48, 49, 53, 68, 79, 126,135, 144, 153, 162, 167, 187, 198, 204, 213, 222, 231, -- not connected 1) the eda (electronic design automation) signal name is used in qimonda simulation models such as ebd (electronic board descrip tion). abbreviation description i standard input pin only. digital levels. o standard output pin only - digital levels. i/o i/o is a bidirectional input/output signal. ai input - analog levels. pwr power gnd ground nc not connected abbreviation description sstl serial stub terminated logic cmos cmos levels od open drain. the corresponding pin has 2 oper ational states, active low and tri-state, and allows multiple devices to share as a wire-or. pin name eda signal name 1) pin no. pin type buffer type function
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 13 11202007-pqti-i4uf figure 1 pin configuration udimm - 240 pin 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 9 5()'4 '4 9 66 '46 '4 9 66 '4 '46 9 66 '4 9 66 '4 '46 9 66 '4 '4 9 66 '46 '4 9 66 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq '4 '46 9 66 '4 '4 9 66 '46 '4 9 66 &%1& '461& 9 66 &%1& 1& &.( %$ 9 '' $ $ 9 '' 9 '' &. 9 '' 1& $$3 9 '' &$6 61& 9 '' 9 66 '4 '46 9 66 '4 '4 9 66 '46 '4 9 66 '4 '46 9 66 '4 '4 9 66 '46 '4 9 66 6&/ 9 77 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq '4 9 66 '46 '4 9 66 '4 '46 9 66 '4 &%1& 9 66 '461& &%1& 9 66 1& 9 '' 1& $ 9 '' $ $ &. 9 '' 9 5()&$ 9 '' %$ :( 9 '' 2'71& 1& '4 9 66 '46 '4 9 66 '4 '46 9 66 '4 '4 9 66 '46 '4 9 66 '4 '46 9 66 '4 6$ 6$ 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 9 66 '4 '0 9 66 '4 '4 9 66 1& '4 9 66 '4 9 66 1& '4 9 66 '4 '0 9 66 '4 '4 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 9 66 1& '4 9 66 '4 '0 9 66 '4 &%1& 9 66 1& &%1& 9 66 5(6(7 9 '' $ $%& 9 '' $ $ 9 '' &. 9 '' $ %$ 5$6 9 ''4 $ 1& '4 9 66 1& '4 9 66 '4 '0 9 66 '4 '4 9 66 1& '4 9 66 '4 '0 9 66 '4 9 ''63' 6'$ 9 77 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq '4 '0 9 66 '4 '4 9 66 1& '4 9 66 &%1& '01& 9 66 &%1& 1& &.(1& $1& 9 '' $ $ 9 '' $ 9 '' &. 1& 9 '' 9 '' 6 2'7 9 '' 9 66 '4 '0 9 66 '4 '4 9 66 1& '4 9 66 '4 '0 9 66 '4 '4 9 66 1& '4 9 66 6$ 9 66 ) 5 2 1 7 6 , ' ( % $ & . 6 , ' ( 033+
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 14 11202007-pqti-i4uf address mapping the connection of the edge connector pins for address bits to the corresponding input pins of the ddr3 sdrams is different between memory rank 0 and memory rank 1. two types of address mapping from the edge connector to the drams are present, standard a nd mirrored, as described in the mapping table below. system software must take care for this mapping when issuing mode register set commands to the ranks of memory on the module. table 7 definition of standard and mirrored address connection mapping table 8 address mapping for unbuffered dimm modules edge connector signal dram pin - standard dram pin - mirrored a0 a0 a0 a1 a1 a1 a2 a2 a2 a3 a3 a4 a4 a4 a3 a5 a5 a6 a6 a6 a5 a7 a7 a8 a8 a8 a7 a9 a9 a9 a10/ap a10/ap a10/ap a11 a11 a11 a12/bc a12/bc a12/bc a13 a13 a13 a14 a14 a14 a15 a15 a15 ba0 ba0 ba1 ba1 ba1 ba0 ba2 ba2 ba2 qimonda part number dimm density type ranks sdram organization rank 0 rank 1 raw card imsh51u03a1f1c 512 mb non-ecc 1 x 8 standard n.a a imsh51e03a1f1c 512 mb ecc 1 x 8 standard n.a d imsh1gu13a1f1c 1024 mb non-ecc 2 x 8 standard mirrored b imsh1ge13a1f1c 1024 mb ecc 2 x 8 standard mirrored e
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 15 11202007-pqti-i4uf 3 operating conditions 3.1 absolute maximum ratings table 9 absolute maximum ratings table 10 environmental parameters attention: stresses greater than those listed under ?abs olute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functi onal operation of the device at these or any other conditions above those indicated in the operational sect ions of this specification is not implied. exposure to absolute maximum rating conditions fo r extended periods may affect reliability. parameter symbol rating unit note min. max. voltage on v dd pin relative to v ss v dd ?0.4 +1.975 v 1) 1) v dd and v ddq must be within 300mv of each other at all times. v refdq and v refca must not be greater than 0.6 x v ddq . when v dd and v ddq are less than 500 mv, v refdq and v refca may be equal or less than 300 mv. voltage on v ddq pin relative to v ss v ddq ?0.4 +1.975 v voltage on any pin relative to v ss v in , v out ?0.4 +1.975 v parameter symbol rating unit note min. max. operating temperature t opr 055 c 1) 1) the component maximum case temperature ( t case ) shall not exceed the value specified in the ddr3 dra m component specification.. operating humidity (relative) h opr 10 90 % storage temperature t stg ?50 +100 c 2) 2) storage temperature is the case surface temperature on the center/top side of the sdram mentioned in qimonda component datash eet. storage humidity (without condensation) h stg 595 % barometric pressure (operating and storage) p bar 69 105 kpascal 3) 3) up to 9850 ft.
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 16 11202007-pqti-i4uf table 11 dram component operating temperature range 3.2 recommended dc operating conditions table 12 dc operating conditions parameter symbol rating unit note min. max. normal operating temperature range t oper 085 c 1)2) 1) operating temperature t oper is the case surface temperature on the center / top side of the sdram mentioned.. 2) the normal temperature range specifies the temperat ures where all sdram spec ification will be supported. extended temperature range 85 95 c 1)3) 3) some application require operation of the dram in the extended temperature range between 85 c and 95 c operating temperature. for more details please refer to qimonda component datasheet. parameter symbol min. typ. max. unit note supply voltage v dd 1.425 1.5 1.575 v 1)2) 1) v ddq tracks with v dd . ac parameters are measured with v dd and v ddq tied together 2) under all conditions v ddq must be less than or equal to v dd . supply voltage for eeprom and thermal sensor v dd.spd 3.03.33.6v 1)2) supply voltage for output v ddq 1.425 1.5 1.575 v 1)2) reference voltage for dq, dm inputs v refdq.dc 0.49 x v dd 0.5 x v dd 0.51 x v dd v 3)4) 3) the ac peak noise on v ref may not allow v ref to deviate from v ref.dc by more than 1% v dd (for reference: approx. 15 mv). 4) for reference: approx. v dd /2 15 mv. reference voltage for add, cmd inputs v refca.dc 0.49 x v dd 0.5 x v dd 0.51 x v dd v 3)4) terminal voltage v tt 0.49 x v dd 0.5 x v dd 0.51 x v dd v external calibration resistor connected from zq pin to ground r zq 237.6 240.0 242.4 ? 5) 5) the external calibration resistor r zq can be time-shared among drams in multi-rank dimms.
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 17 11202007-pqti-i4uf 4 speed bins and timing parameters ac timings are provided with ck/ck and dqs/dqs differential slew rate of 2.0 v/ns. timings are further provided for calibrated ocd driv e strength. the ck/ck input reference level (for timing referenced to ck / ck ) is the point at which ck and ck cross.the dqs/dqs reference level (for timing referenced to dqs/dqs ) is the point at which dqs and dqs cross.inputs are not re cognized as valid until v ref stabilizes. during the period before v ref.ca and v refdq stabilizes, cke = 0.2 x v ddq is recognized as low. the output timing reference voltage level is v tt .for details of all relevant ac timing parameters see the qimonda ddr3 component datasheet. 4.1 speed bins the following tables show ddr3 speed bins and relevant timing parameters. other timi ng parameters are provided in the following chapter. the absolute specification for all speed bins is t oper and v dd = v ddq = 1.5 v +/-0.075 v. in addition the following general notes apply. general notes for speed bins: ? the cl setting and cwl setting result in t ck.avg.min and t ck.avg.max requirements. when making a selection of t ck.avg , both need to be fulfiled: requirements from cl setting as well as requirements from cwl setting. ? t ck.avg.min limits: since cas latency is not purely analog - data and strobe output are syn chronized by the dll - all possible intermediate frequencies may not be provided. an application should use the next smaller standard t ck.avg value (2.5, 1.875, 1.5, or 1. 25 ns) when calculating cl [nck] = t aa [ns] / t ck.avg [ns], rounding up to the next ?supported cl?. ? t ck.avg.max limits: calculate t ck.avg = t aa.max / clselected and round the resulting t ck.avg down to the next valid speed bin limit (i.e. 3.3 ns or 2.5 ns or 1.875 ns or 1.25 ns). this result is t ck.avg.max corresponding to clselected. ? ?reserved? settings are not a llowed. user must program a different value. ? any ddr3-1066 speed bin also supports functional operation at lower frequencies as shown in the tables which are not subject to production tests but verified by design/characterization. ? any ddr3-1333 speed bin also supports functional operation at lower frequencies as shown in the tables which are not subject to production tests but verified by design/characterization. ? any ddr3-1600 speed bin also supports functional operation at lower frequencies as shown in the tables which are not subject to production tests but verified by design/characterization. table 13 ddr3-800 speed bins speed bin ddr3-800d ddr3-800e unit note cl- n rcd - n rp 5-5-5 6-6-6 qimonda part number extension -08d -08e parameter symbol min. max. min. max. internal read command to first data t aa 12.5 20.0 15.0 20.0 ns 1) act to internal read or write delay time t rcd 12.5 ? 15.0 ? ns 1) pre command period t rp 12.5 ? 15.0 ? ns 1) act to act or ref command period t rc 50.0 ? 52.5 ? ns 1) supported cl settings sup_cl 5, 6 6 n ck 1) supported cwl settings sup_cwl 5 5 n ck 1)
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 18 11202007-pqti-i4uf table 14 ddr3-1066 speed bins average clock period with cl = 5; cwl = 5 t ck.avg.cl05.cwl05 2.5 3.3 reserved ns 1)2) average clock period with cl = 6; cwl = 5 t ck.avg.cl06.cwl05 2.5 3.3 2.5 3.3 ns 1)2) 1) please refer to "general notes for speed bins" at beginning of this chapter. 2) max. limits are exclusive. e.g. if t ck.avg.max value is 2.5 ns, t ck.avg needs to be < 2.5 ns. speed bin ddr3-1066e ddr3-1066f ddr3-1066g unit note cl- n rcd - n rp 6-6-6 7-7-7 8-8-8 qimonda part number extension -10e -10f -10g parameter symbol min. max. min. max. min. max. internal read command to first data t aa 11.25 20.0 13.125 20.0 15.0 20.0 ns 1) 1) please refer to "general notes for speed bins" at beginning of this chapter. act to internal read or write delay time t rcd 11.25 ? 13.125 ? 15.0 ? ns 1) pre command period t rp 11.25 ? 13.125 ? 15.0 ? ns 1) act to act or ref command period t rc 48.75 ? 50.625 ? 52.5 ? ns 1) supported cl settings sup_cl 5, 6, 7, 8 6, 7, 8 6, 8 n ck 1) supported cwl settings sup_cwl 5, 6 5, 6 5, 6 n ck 1) average clock period with cl = 5; cwl = 5 t ck.avg.cl05.cwl05 2.5 3.3 reserved reserved ns 1)2) 2) max. limits are exclusive. e.g. if t ck.avg.max value is 2.5 ns, t ck.avg needs to be < 2.5 ns. average clock period with cl = 5; cwl = 6 t ck.avg.cl05.cwl06 reserved reserved reserved ns 1)2) average clock period with cl = 6; cwl = 5 t ck.avg.cl06.cwl05 2.5 3.3 2.5 3.3 2.5 3.3 ns 1)2) average clock period with cl = 6; cwl = 6 t ck.avg.cl06.cwl06 1.875 2.5 reserved reserved ns 1)2) average clock period with cl = 7; cwl = 5 t ck.avg.cl07.cwl05 reserved reserved reserved ns 1)2) average clock period with cl = 7; cwl = 6 t ck.avg.cl07.cwl06 1.875 2.5 1.875 2.5 reserved ns 1)2) average clock period with cl = 8; cwl = 5 t ck.avg.cl08.cwl05 reserved reserved reserved ns 1)2) average clock period with cl = 8; cwl = 6 t ck.avg.cl08.cwl06 1.875 2.5 1.875 2.5 1.875 2.5 ns 1)2) speed bin ddr3-800d ddr3-800e unit note cl- n rcd - n rp 5-5-5 6-6-6 qimonda part number extension -08d -08e parameter symbol min. max. min. max.
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 19 11202007-pqti-i4uf table 15 ddr3-1333 speed bins speed bin ddr3- 1333g ddr3- 1333h ddr3-1333j unit note cl- n rcd - n rp 8-8-8 9-9-9 10-10-10 qimonda part number extension -13g -13h -13j parameter symbol min. max. min. max. min. max. internal read command to first data t aa 12.0 20.0 13.5 20.0 15.0 20.0 ns 1) 1) please refer to "general notes for speed bins" at beginning of this chapter. act to internal read or write delay time t rcd 12.0 ? 13.5 ? 15.0 ? ns 1) pre command period t rp 12.0 ? 13.5 ? 15.0 ? ns 1) act to act or ref command period t rc 48.0 ? 49.5 ? 51.0 ? ns 1) supported cl settings s up_cl 5, 6, 7, 8, 9, 10 6, 8, 9, 10 6, 8, 10 n ck 1) supported cwl settings sup_cwl 5, 6, 7 5, 6, 7 5, 6, 7 n ck 1) average clock period with cl = 5; cwl = 5 t ck.avg.cl05.cwl05 2.5 3.3 reserved reserved ns 1)2) 2) max. limits are exclusive. e.g. if t ck.avg.max value is 2.5 ns, t ck.avg needs to be < 2.5 ns. average clock period with cl = 5; cwl = 6 t ck.avg.cl05.cwl06 reserved reserved reserved ns 1)2) average clock period with cl = 5; cwl = 7 t ck.avg.cl05.cwl07 reserved reserved reserved ns 1)2) average clock period with cl = 6; cwl = 5 t ck.avg.cl06.cwl05 2.5 3.3 2.5 3.3 2.5 3.3 ns 1)2) average clock period with cl = 6; cwl = 6 t ck.avg.cl06.cwl06 reserved reserved reserved ns 1)2) average clock period with cl = 6; cwl = 7 t ck.avg.cl06.cwl07 reserved reserved reserved ns 1)2) average clock period with cl = 7; cwl = 5 t ck.avg.cl07.cwl05 reserved reserved reserved ns 1)2) average clock period with cl = 7; cwl = 6 t ck.avg.cl07.cwl06 1.875 2.5 reserved reserved ns 1)2) average clock period with cl = 7; cwl = 7 t ck.avg.cl07.cwl07 reserved reserved reserved ns 1)2) average clock period with cl = 8; cwl = 5 t ck.avg.cl08.cwl05 reserved reserved reserved ns 1)2) average clock period with cl = 8; cwl = 6 t ck.avg.cl08.cwl06 1.875 2.5 1.875 2.5 1.875 2.5 ns 1)2) average clock period with cl = 8; cwl = 7 t ck.avg.cl08.cwl07 1.5 1.875 reserved reserved ns 1)2) average clock period with cl = 9; cwl = 5 t ck.avg.cl09.cwl05 reserved reserved reserved ns 1)2) average clock period with cl = 9; cwl = 6 t ck.avg.cl09.cwl06 reserved reserved reserved ns 1)2) average clock period with cl = 9; cwl = 7 t ck.avg.cl09.cwl07 1.5 1.875 1.5 1.875 reserved ns 1)2) average clock period with cl = 10; cwl = 5 t ck.avg.cl10.cwl05 reserved reserved reserved ns 1)2) average clock period with cl = 10; cwl = 6 t ck.avg.cl10.cwl06 reserved reserved reserved ns 1)2) average clock period with cl = 10; cwl = 7 t ck.avg.cl10.cwl07 1.5 1.875 1.5 1.875 1.5 1.875 ns 1)2)
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 20 11202007-pqti-i4uf table 16 ddr3-1600 speed bins speed bin ddr3-1600h ddr3-1600j unit note cl- n rcd - n rp 9-9-9 10-10-10 qimonda part number extension -16h -16j parameter symbol min. max. min. max. internal read command to first data t aa 11.25 20.0 12.5 20.0 ns 1) 1) please refer to "general notes for speed bins" at beginning of this chapter. act to internal read or write delay time t rcd 11.25 ? 12.5 ? ns 1) pre command period t rp 11.25 ? 12.5 ? ns 1) act to act or ref command period t rc 46.25 ? 47.5 ? ns 1) supported cl settings sup_cl 5, 6, 7, 8, 9, 10 5, 6, 7, 8, 9, 10 n ck 1) supported cwl settings sup_cwl 5, 6, 7, 8 5, 6, 7, 8 n ck 1) average clock period with cl = 5; cwl = 5 t ck.avg.cl05.cwl05 2.5 3.3 2.5 3.3 ns 1)2) 2) max. limits are exclusive. e.g. if t ck.avg.max value is 2.5 ns, t ck.avg needs to be < 2.5 ns. average clock period with cl = 5; cwl = 6 t ck.avg.cl05.cwl06 reserved reserved ns 1)2) average clock period with cl = 5; cwl = 7 t ck.avg.cl05.cwl07 reserved reserved ns 1)2) average clock period with cl = 5; cwl = 8 t ck.avg.cl05.cwl08 reserved reserved ns 1)2) average clock period with cl = 6; cwl = 5 t ck.avg.cl06.cwl05 2.5 3.3 2.5 3.3 ns 1)2) average clock period with cl = 6; cwl = 6 t ck.avg.cl06.cwl06 1.875 2.5 reserved ns 1)2) average clock period with cl = 6; cwl = 7 t ck.avg.cl06.cwl07 reserved reserved ns 1)2) average clock period with cl = 6; cwl = 8 t ck.avg.cl06.cwl08 reserved reserved ns 1)2) average clock period with cl = 7; cwl = 5 t ck.avg.cl07.cwl05 reserved reserved ns 1)2) average clock period with cl = 7; cwl = 6 t ck.avg.cl07.cwl06 1.875 2.5 1.875 2.5 ns 1)2) average clock period with cl = 7; cwl = 7 t ck.avg.cl07.cwl07 reserved reserved ns 1)2) average clock period with cl = 7; cwl = 8 t ck.avg.cl07.cwl08 reserved reserved ns 1)2) average clock period with cl = 8; cwl = 5 t ck.avg.cl08.cwl05 reserved reserved ns 1)2) average clock period with cl = 8; cwl = 6 t ck.avg.cl08.cwl06 1.875 2.5 1.875 2.5 ns 1)2) average clock period with cl = 8; cwl = 7 t ck.avg.cl08.cwl07 1.5 1.875 reserved ns 1)2) average clock period with cl = 8; cwl = 8 t ck.avg.cl08.cwl08 reserved reserved ns 1)2) average clock period with cl = 9; cwl = 5 t ck.avg.cl09.cwl05 reserved reserved ns 1)2) average clock period with cl = 9; cwl = 6 t ck.avg.cl09.cwl06 reserved reserved ns 1)2) average clock period with cl = 9; cwl = 7 t ck.avg.cl09.cwl07 1.5 1.875 1.5 1.875 ns 1)2) average clock period with cl = 9; cwl = 8 t ck.avg.cl09.cwl08 1.25 1.5 reserved ns 1)2) average clock period with cl = 10; cwl = 5 t ck.avg.cl10.cwl05 reserved reserved ns 1)2) average clock period with cl = 10; cwl = 6 t ck.avg.cl10.cwl06 reserved reserved ns 1)2) average clock period with cl = 10; cwl = 7 t ck.avg.cl10.cwl07 1.5 1.875 1.5 1.875 ns 1)2) average clock period with cl = 10; cwl = 8 t ck.avg.cl10.cwl08 1.25 1.5 1.25 1.5 ns 1)2)
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 21 11202007-pqti-i4uf 5 spd codes this chapter lists all hexadecimal byte values stored in the eeprom of the products described in this data sheet. spd stands for serial presence detect. all values with xx in the table are module specific bytes which are defined during production. list of spd code tables ? table 17 ?spd codes for imsh51u03a1f 1c?[08d/08e/10e/10f/10g]? on page 21 ? table 18 ?spd codes for imsh51u03a1f1c?[13g/13h/13j/16h/16j]? on page 25 ? table 19 ?spd codes for imsh51e03a1f 1c?[08d/08e/10e/10f/10g]? on page 29 ? table 20 ?spd codes for imsh51e03a1f1c?[13g/13h/13j/16h/16j]? on page 33 ? table 21 ?spd codes for imsh1gu13a1f1c?[08d/08e/10e/10f/10g]? on page 37 ? table 22 ?spd codes for imsh1gu13a1f1c?[13g/13h/13j/16h/16j]? on page 41 ? table 23 ?spd codes for imsh1ge13a1f 1c?[08d/08e/10e/10f/10g]? on page 45 ? table 24 ?spd codes for imsh1ge13a1f1c?[13g/13h/13j/16h/16j]? on page 49 table 17 spd codes for imsh51u03a1f1 c?[08d/08e/10e/10f/10g] product type imsh51u03a1f1c?08d imsh51u03a1f1c?08e imsh51u03a1f1c?10e imsh51u03a1f1c?10f imsh51u03a1f1c?10g organization 512mb 512mb 512mb 512mb 512mb 64 64 64 64 64 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) label code pc3? 6400u?5 pc3? 6400u?6 pc3? 8500u?6 pc3? 8500u?7 pc3? 8500u?8 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex 0 # of spd bytes utilized / # of bytes in spd / crc 92 92 92 92 92 1 spd revision 05 05 05 05 05 2 sdram technology key byte 0b 0b 0b 0b 0b 3 dimm module type 02 02 02 02 02 4 sdram density and banks 01 01 01 01 01 5 sdram addressing 09 09 09 09 09 6 module physical attributes 00 00 00 00 00 7 module organization 01 01 01 01 01
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 22 11202007-pqti-i4uf 8 module memory bus width 03 03 03 03 03 9 fine time base (ftb) dividend and divisor 52 52 52 52 52 10 medium time base (mtb) dividend 01 01 01 01 01 11 medium time base (mtb) divisor 08 08 08 08 08 12 minimum sdram cycle time ( t ck.min ) 14140f0f0f 13 reserved 00 00 00 00 00 14 cas latencies supported - lsb 06 04 1e 1c 14 15 cas latencies supported - msb 00 00 00 00 00 16 minimum cas latency time (t ck.min ) 64785a6978 17 minimum write recovery time (t wr.min ) 7878787878 18 minimum ras# tocas# delay time (t rcd.min ) 64785a6978 19 minimum row active to row active delay time (t rrd.min ) 50 50 3c 3c 3c 20 minimum row prechargetime (t rp.min ) 64785a6978 21 upper nibbles fo r t ras and t rc 11 11 11 11 11 22 minimum active to precharge time (t ras.min ), lsb2c2c2c2c2c 23 minimum active to active/refresh time (t rc.min ), lsb90a48695a4 24 minimum refresh recovery time (t rfc.min ), lsbd0d0d0d0d0 25 minimum refresh recovery time (t rfc.min ), msb0202020202 26 minimum internal write to read command delay time (t wtr.min ) 3c 3c 3c 3c 3c 27 minimum internal read to precharge command delay time (t rtp.min ), msb 3c 3c 3c 3c 3c 28 upper nibble for t faw 01 01 01 01 01 29 minimum four activate window delay time (t faw.min )40402c2c2c 30 sdram output drivers supported 02 02 02 02 02 product type imsh51u03a1f1c?08d imsh51u03a1f1c?08e imsh51u03a1f1c?10e imsh51u03a1f1c?10f imsh51u03a1f1c?10g organization 512mb 512mb 512mb 512mb 512mb 64 64 64 64 64 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) label code pc3? 6400u?5 pc3? 6400u?6 pc3? 8500u?6 pc3? 8500u?7 pc3? 8500u?8 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 23 11202007-pqti-i4uf 31sdram refresh options 8181818181 32 - 59 reserved 00 00 00 00 00 60 module nominal height 10 10 10 10 10 61 module maximum thickness 01 01 01 01 01 62 raw card used 00 00 00 00 00 63 address mapping from edge connector to dram 00 00 00 00 00 64 - 116 reserved 00 00 00 00 00 117 dimm manufacturer?s id code lsb 85 85 85 85 85 118 dimm manufacturer?s id code msb 51 51 51 51 51 119 module manufacturing location xx xx xx xx xx 120 - 121 module manufacturing date xx xx xx xx xx 122 - 125 module serial number xx xx xx xx xx 126 cyclical redundancy code lsb 7f 70 a9 e8 8b 127 cyclical redundancy code msb 56 a7 57 fe 0b 128 product type, char 1 49 49 49 49 49 129 product type, char 2 4d 4d 4d 4d 4d 130 product type, char 3 53 53 53 53 53 131 product type, char 4 48 48 48 48 48 132 product type, char 5 35 35 35 35 35 133 product type, char 6 31 31 31 31 31 134 product type, char 7 55 55 55 55 55 135 product type, char 8 30 30 30 30 30 136 product type, char 9 33 33 33 33 33 137 product type, char 10 41 41 41 41 41 product type imsh51u03a1f1c?08d imsh51u03a1f1c?08e imsh51u03a1f1c?10e imsh51u03a1f1c?10f imsh51u03a1f1c?10g organization 512mb 512mb 512mb 512mb 512mb 64 64 64 64 64 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) label code pc3? 6400u?5 pc3? 6400u?6 pc3? 8500u?6 pc3? 8500u?7 pc3? 8500u?8 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 24 11202007-pqti-i4uf 138 product type, char 11 31 31 31 31 31 139 product type, char 12 46 46 46 46 46 140 product type, char 13 31 31 31 31 31 141 product type, char 14 43 43 43 43 43 142 product type, char 15 2d 2d 2d 2d 2d 143 product type, char 16 30 30 31 31 31 144 product type, char 17 38 38 30 30 30 145 product type, char 18 44 45 45 46 47 146 module revision code, lsb 4x 4x 2x 4x 4x 147 module revision code, msb xx xx xx xx xx 148 dram manufacturer?s id code, lsb 85 85 85 85 85 149 dram manufacturer?s id code, msb 51 51 51 51 51 150 - 175 manufactures?s specific data 00 00 00 00 00 176 - 255 blank for customer use 0000000000 product type imsh51u03a1f1c?08d imsh51u03a1f1c?08e imsh51u03a1f1c?10e imsh51u03a1f1c?10f imsh51u03a1f1c?10g organization 512mb 512mb 512mb 512mb 512mb 64 64 64 64 64 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) label code pc3? 6400u?5 pc3? 6400u?6 pc3? 8500u?6 pc3? 8500u?7 pc3? 8500u?8 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 25 11202007-pqti-i4uf table 18 spd codes for imsh51u03a1f 1c?[13g/13h/13j/16h/16j] product type imsh51u03a1f1c?13g imsh51u03a1f1c?13h imsh51u03a1f1c?13j imsh51u03a1f1c?16h imsh51u03a1f1c?16j organization 512mb 512mb 512mb 512mb 512mb 64 64 64 64 64 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( x8) 1 rank ( x8) label code pc3? 10600u? 8 pc3? 10600u? 9 pc3? 10600u? 11 pc3? 12800u? 9 pc3? 12800u? 11 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex 0 # of spd bytes utilized / # of bytes in spd / crc 92 92 92 92 92 1 spd revision 05 05 05 05 05 2 sdram technology key byte 0b 0b 0b 0b 0b 3 dimm module type 02 02 02 02 02 4 sdram density and banks 01 01 01 01 01 5 sdram addressing 09 09 09 09 09 6 module physical attributes 00 00 00 00 00 7 module organization 01 01 01 01 01 8 module memory bus width 03 03 03 03 03 9 fine time base (ftb) dividend and divisor 52 52 52 52 52 10 medium time base (mtb) dividend 01 01 01 01 01 11 medium time base (mtb) divisor 08 08 08 08 08 12 minimum sdram cycle time ( t ck.min ) 0c0c0c0a0a 13 reserved 00 00 00 00 00 14 cas latencies supported - lsb 36 3e 34 7e 7e 15 cas latencies supported - msb 00 00 00 00 00 16 minimum cas latency time (t ck.min ) 606c785a64 17 minimum write recovery time (t wr.min ) 7878787878 18 minimum ras# tocas# delay time (t rcd.min ) 606c785a64 19 minimum row active to row active delay time (t rrd.min ) 30 30 30 30 30 20 minimum row prechargetime (t rp.min ) 606c785a64
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 26 11202007-pqti-i4uf 21 upper nibbles fo r t ras and t rc 11 11 11 11 11 22 minimum active to precharge time (t ras.min ), lsb2020201818 23 minimum active to active/refresh time (t rc.min ), lsb808c98727c 24 minimum refresh recovery time (t rfc.min ), lsbd0d0d0d0d0 25 minimum refresh recovery time (t rfc.min ), msb0202020202 26 minimum internal write to read command delay time (t wtr.min ) 3c 3c 3c 3c 3c 27 minimum internal read to precharge command delay time (t rtp.min ), msb 3c 3c 3c 3c 3c 28 upper nibble for t faw 00 00 00 00 00 29 minimum four activate window delay time (t faw.min )f0f0f0f0f0 30 sdram output drivers supported 02 02 02 02 02 31sdram refresh options 8181818181 32 - 59 reserved 00 00 00 00 00 60 module nominal height 10 10 10 10 10 61 module maximum thickness 01 01 01 01 01 62 raw card used 00 00 00 00 00 63 address mapping from edge connector to dram 00 00 00 00 00 64 - 116 reserved 00 00 00 00 00 117 dimm manufacturer?s id code lsb 85 85 85 85 85 118 dimm manufacturer?s id code msb 51 51 51 51 51 119 module manufacturing location xx xx xx xx xx 120 - 121 module manufacturing date xx xx xx xx xx product type imsh51u03a1f1c?13g imsh51u03a1f1c?13h imsh51u03a1f1c?13j imsh51u03a1f1c?16h imsh51u03a1f1c?16j organization 512mb 512mb 512mb 512mb 512mb 64 64 64 64 64 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( x8) 1 rank ( x8) label code pc3? 10600u? 8 pc3? 10600u? 9 pc3? 10600u? 11 pc3? 12800u? 9 pc3? 12800u? 11 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 27 11202007-pqti-i4uf 122 - 125 module serial number xx xx xx xx xx 126 cyclical redundancy code lsb f5 8c d8 28 29 127 cyclical redundancy code msb 52 f2 4e 86 88 128 product type, char 1 49 49 49 49 49 129 product type, char 2 4d 4d 4d 4d 4d 130 product type, char 3 53 53 53 53 53 131 product type, char 4 48 48 48 48 48 132 product type, char 5 35 35 35 35 35 133 product type, char 6 31 31 31 31 31 134 product type, char 7 55 55 55 55 55 135 product type, char 8 30 30 30 30 30 136 product type, char 9 33 33 33 33 33 137 product type, char 10 41 41 41 41 41 138 product type, char 11 31 31 31 31 31 139 product type, char 12 46 46 46 46 46 140 product type, char 13 31 31 31 31 31 141 product type, char 14 43 43 43 43 43 142 product type, char 15 2d 2d 2d 2d 2d 143 product type, char 16 31 31 31 31 31 144 product type, char 17 33 33 33 36 36 145 product type, char 18 47 48 4a 48 4a 146 module revision code, lsb 1x 4x 4x 0x 0x 147 module revision code, msb xx xx xx xx xx 148 dram manufacturer?s id code, lsb 85 85 85 85 85 product type imsh51u03a1f1c?13g imsh51u03a1f1c?13h imsh51u03a1f1c?13j imsh51u03a1f1c?16h imsh51u03a1f1c?16j organization 512mb 512mb 512mb 512mb 512mb 64 64 64 64 64 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( x8) 1 rank ( x8) label code pc3? 10600u? 8 pc3? 10600u? 9 pc3? 10600u? 11 pc3? 12800u? 9 pc3? 12800u? 11 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 28 11202007-pqti-i4uf 149 dram manufacturer?s id code, msb 51 51 51 51 51 150 - 175 manufactures?s specific data 00 00 00 00 00 176 - 255 blank for customer use 0000000000 product type imsh51u03a1f1c?13g imsh51u03a1f1c?13h imsh51u03a1f1c?13j imsh51u03a1f1c?16h imsh51u03a1f1c?16j organization 512mb 512mb 512mb 512mb 512mb 64 64 64 64 64 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( x8) 1 rank ( x8) label code pc3? 10600u? 8 pc3? 10600u? 9 pc3? 10600u? 11 pc3? 12800u? 9 pc3? 12800u? 11 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 29 11202007-pqti-i4uf table 19 spd codes for imsh51e03a1f1c?[08d/08e/10e/10f/10g] product type imsh51e03a1f1c?08d imsh51e03a1f1c?08e imsh51e03a1f1c?10e imsh51e03a1f1c?10f imsh51e03a1f1c?10g organization 512mb 512mb 512mb 512mb 512mb 72 72 72 72 72 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) label code pc3? 6400e?5 pc3? 6400e?6 pc3? 8500e?6 pc3? 8500e?7 pc3? 8500e?8 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex 0 # of spd bytes utilized / # of bytes in spd / crc 92 92 92 92 92 1 spd revision 05 05 05 05 05 2 sdram technology key byte 0b 0b 0b 0b 0b 3 dimm module type 02 02 02 02 02 4 sdram density and banks 01 01 01 01 01 5 sdram addressing 09 09 09 09 09 6 module physical attributes 00 00 00 00 00 7 module organization 01 01 01 01 01 8 module memory bus width 0b 0b 0b 0b 0b 9 fine time base (ftb) dividend and divisor 52 52 52 52 52 10 medium time base (mtb) dividend 01 01 01 01 01 11 medium time base (mtb) divisor 08 08 08 08 08 12 minimum sdram cycle time ( t ck.min ) 14140f0f0f 13 reserved 00 00 00 00 00 14 cas latencies supported - lsb 06 04 1e 1c 14 15 cas latencies supported - msb 00 00 00 00 00 16 minimum cas latency time (t ck.min ) 64785a6978 17 minimum write recovery time (t wr.min ) 7878787878 18 minimum ras# tocas# delay time (t rcd.min ) 64785a6978 19 minimum row active to row active delay time (t rrd.min ) 50 50 3c 3c 3c 20 minimum row prechargetime (t rp.min ) 64785a6978 21 upper nibbles fo r t ras and t rc 11 11 11 11 11
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 30 11202007-pqti-i4uf 22 minimum active to precharge time (t ras.min ), lsb2c2c2c2c2c 23 minimum active to active/refresh time (t rc.min ), lsb90a48695a4 24 minimum refresh recovery time (t rfc.min ), lsbd0d0d0d0d0 25 minimum refresh recovery time (t rfc.min ), msb0202020202 26 minimum internal write to read command delay time (t wtr.min ) 3c 3c 3c 3c 3c 27 minimum internal read to precharge command delay time (t rtp.min ), msb 3c 3c 3c 3c 3c 28 upper nibble for t faw 01 01 01 01 01 29 minimum four activate window delay time (t faw.min )40402c2c2c 30 sdram output drivers supported 02 02 02 02 02 31sdram refresh options 8181818181 32 - 59 reserved 00 00 00 00 00 60 module nominal height 10 10 10 10 10 61 module maximum thickness 01 01 01 01 01 62 raw card used 03 03 03 03 03 63 address mapping from edge connector to dram 00 00 00 00 00 64 - 116 reserved 00 00 00 00 00 117 dimm manufacturer?s id code lsb 85 85 85 85 85 118 dimm manufacturer?s id code msb 51 51 51 51 51 119 module manufacturing location xx xx xx xx xx 120 - 121 module manufacturing date xx xx xx xx xx 122 - 125 module serial number xx xx xx xx xx 126 cyclical redundancy code lsb ab a4 7d 3c 5f product type imsh51e03a1f1c?08d imsh51e03a1f1c?08e imsh51e03a1f1c?10e imsh51e03a1f1c?10f imsh51e03a1f1c?10g organization 512mb 512mb 512mb 512mb 512mb 72 72 72 72 72 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) label code pc3? 6400e?5 pc3? 6400e?6 pc3? 8500e?6 pc3? 8500e?7 pc3? 8500e?8 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 31 11202007-pqti-i4uf 127 cyclical redundancy code msb 89 78 88 21 d4 128 product type, char 1 49 49 49 49 49 129 product type, char 2 4d 4d 4d 4d 4d 130 product type, char 3 53 53 53 53 53 131 product type, char 4 48 48 48 48 48 132 product type, char 5 35 35 35 35 35 133 product type, char 6 31 31 31 31 31 134 product type, char 7 45 45 45 45 45 135 product type, char 8 30 30 30 30 30 136 product type, char 9 33 33 33 33 33 137 product type, char 10 41 41 41 41 41 138 product type, char 11 31 31 31 31 31 139 product type, char 12 46 46 46 46 46 140 product type, char 13 31 31 31 31 31 141 product type, char 14 43 43 43 43 43 142 product type, char 15 2d 2d 2d 2d 2d 143 product type, char 16 30 30 31 31 31 144 product type, char 17 38 38 30 30 30 145 product type, char 18 44 45 45 46 47 146 module revision code, lsb 1x 1x 1x 1x 1x 147 module revision code, msb xx xx xx xx xx 148 dram manufacturer?s id code, lsb 85 85 85 85 85 149 dram manufacturer?s id code, msb 51 51 51 51 51 product type imsh51e03a1f1c?08d imsh51e03a1f1c?08e imsh51e03a1f1c?10e imsh51e03a1f1c?10f imsh51e03a1f1c?10g organization 512mb 512mb 512mb 512mb 512mb 72 72 72 72 72 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) label code pc3? 6400e?5 pc3? 6400e?6 pc3? 8500e?6 pc3? 8500e?7 pc3? 8500e?8 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 32 11202007-pqti-i4uf 150 - 175 manufactures?s specific data 00 00 00 00 00 176 - 255 blank for customer use 0000000000 product type imsh51e03a1f1c?08d imsh51e03a1f1c?08e imsh51e03a1f1c?10e imsh51e03a1f1c?10f imsh51e03a1f1c?10g organization 512mb 512mb 512mb 512mb 512mb 72 72 72 72 72 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) label code pc3? 6400e?5 pc3? 6400e?6 pc3? 8500e?6 pc3? 8500e?7 pc3? 8500e?8 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 33 11202007-pqti-i4uf table 20 spd codes for imsh51e03a1f 1c?[13g/13h/13j/16h/16j] product type imsh51e03a1f1c?13g imsh51e03a1f1c?13h imsh51e03a1f1c?13j imsh51e03a1f1c?16h imsh51e03a1f1c?16j organization 512mb 512mb 512mb 512mb 512mb 72 72 72 72 72 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( x8) 1 rank ( x8) label code pc3? 10600e?8 pc3? 10600e?9 pc3? 10600e? 11 pc3? 12800e?9 pc3? 12800e? 11 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex 0 # of spd bytes utilized / # of bytes in spd / crc 92 92 92 92 92 1 spd revision 05 05 05 05 05 2 sdram technology key byte 0b 0b 0b 0b 0b 3 dimm module type 02 02 02 02 02 4 sdram density and banks 01 01 01 01 01 5 sdram addressing 09 09 09 09 09 6 module physical attributes 00 00 00 00 00 7 module organization 01 01 01 01 01 8 module memory bus width 0b 0b 0b 0b 0b 9 fine time base (ftb) dividend and divisor 52 52 52 52 52 10 medium time base (mtb) dividend 01 01 01 01 01 11 medium time base (mtb) divisor 08 08 08 08 08 12 minimum sdram cycle time ( t ck.min ) 0c0c0c0a0a 13 reserved 00 00 00 00 00 14 cas latencies supported - lsb 36 3e 34 7e 7e 15 cas latencies supported - msb 00 00 00 00 00 16 minimum cas latency time (t ck.min ) 606c785a64 17 minimum write recovery time (t wr.min ) 7878787878 18 minimum ras# tocas# delay time (t rcd.min ) 606c785a64 19 minimum row active to row active delay time (t rrd.min ) 30 30 30 30 30 20 minimum row prechargetime (t rp.min ) 606c785a64
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 34 11202007-pqti-i4uf 21 upper nibbles fo r t ras and t rc 11 11 11 11 11 22 minimum active to precharge time (t ras.min ), lsb2020201818 23 minimum active to active/refresh time (t rc.min ), lsb808c98727c 24 minimum refresh recovery time (t rfc.min ), lsbd0d0d0d0d0 25 minimum refresh recovery time (t rfc.min ), msb0202020202 26 minimum internal write to read command delay time (t wtr.min ) 3c 3c 3c 3c 3c 27 minimum internal read to precharge command delay time (t rtp.min ), msb 3c 3c 3c 3c 3c 28 upper nibble for t faw 00 00 00 00 00 29 minimum four activate window delay time (t faw.min )f0f0f0f0f0 30 sdram output drivers supported 02 02 02 02 02 31sdram refresh options 8181818181 32 - 59 reserved 00 00 00 00 00 60 module nominal height 10 10 10 10 10 61 module maximum thickness 01 01 01 01 01 62 raw card used 03 03 03 03 03 63 address mapping from edge connector to dram 00 00 00 00 00 64 - 116 reserved 00 00 00 00 00 117 dimm manufacturer?s id code lsb 85 85 85 85 85 118 dimm manufacturer?s id code msb 51 51 51 51 51 119 module manufacturing location xx xx xx xx xx 120 - 121 module manufacturing date xx xx xx xx xx product type imsh51e03a1f1c?13g imsh51e03a1f1c?13h imsh51e03a1f1c?13j imsh51e03a1f1c?16h imsh51e03a1f1c?16j organization 512mb 512mb 512mb 512mb 512mb 72 72 72 72 72 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( x8) 1 rank ( x8) label code pc3? 10600e?8 pc3? 10600e?9 pc3? 10600e? 11 pc3? 12800e?9 pc3? 12800e? 11 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 35 11202007-pqti-i4uf 122 - 125 module serial number xx xx xx xx xx 126 cyclical redundancy code lsb 21 58 0c fc fd 127 cyclical redundancy code msb 8d 2d 91 59 57 128 product type, char 1 49 49 49 49 49 129 product type, char 2 4d 4d 4d 4d 4d 130 product type, char 3 53 53 53 53 53 131 product type, char 4 48 48 48 48 48 132 product type, char 5 35 35 35 35 35 133 product type, char 6 31 31 31 31 31 134 product type, char 7 45 45 45 45 45 135 product type, char 8 30 30 30 30 30 136 product type, char 9 33 33 33 33 33 137 product type, char 10 41 41 41 41 41 138 product type, char 11 31 31 31 31 31 139 product type, char 12 46 46 46 46 46 140 product type, char 13 31 31 31 31 31 141 product type, char 14 43 43 43 43 43 142 product type, char 15 2d 2d 2d 2d 2d 143 product type, char 16 31 31 31 31 31 144 product type, char 17 33 33 33 36 36 145 product type, char 18 47 48 4a 48 4a 146 module revision code, lsb 1x 1x 1x 0x 0x 147 module revision code, msb xx xx xx xx xx 148 dram manufacturer?s id code, lsb 85 85 85 85 85 product type imsh51e03a1f1c?13g imsh51e03a1f1c?13h imsh51e03a1f1c?13j imsh51e03a1f1c?16h imsh51e03a1f1c?16j organization 512mb 512mb 512mb 512mb 512mb 72 72 72 72 72 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( x8) 1 rank ( x8) label code pc3? 10600e?8 pc3? 10600e?9 pc3? 10600e? 11 pc3? 12800e?9 pc3? 12800e? 11 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 36 11202007-pqti-i4uf 149 dram manufacturer?s id code, msb 51 51 51 51 51 150 - 175 manufactures?s specific data 00 00 00 00 00 176 - 255 blank for customer use 0000000000 product type imsh51e03a1f1c?13g imsh51e03a1f1c?13h imsh51e03a1f1c?13j imsh51e03a1f1c?16h imsh51e03a1f1c?16j organization 512mb 512mb 512mb 512mb 512mb 72 72 72 72 72 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( x8) 1 rank ( x8) label code pc3? 10600e?8 pc3? 10600e?9 pc3? 10600e? 11 pc3? 12800e?9 pc3? 12800e? 11 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 37 11202007-pqti-i4uf table 21 spd codes for imsh1gu13a1f1c?[08d/08e/10e/10f/10g] product type imsh1gu13a1f1c?08d imsh1gu13a1f1c?08e imsh1gu13a1f1c?10e imsh1gu13a1f1c?10f imsh1gu13a1f1c?10g organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 1 gbyte 64 64 64 64 64 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3? 6400u?5 pc3? 6400u?6 pc3? 8500u?6 pc3? 8500u?7 pc3? 8500u?8 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex 0 # of spd bytes utilized / # of bytes in spd / crc 92 92 92 92 92 1 spd revision 05 05 05 05 05 2 sdram technology key byte 0b 0b 0b 0b 0b 3 dimm module type 02 02 02 02 02 4 sdram density and banks 01 01 01 01 01 5 sdram addressing 09 09 09 09 09 6 module physical attributes 00 00 00 00 00 7 module organization 09 09 09 09 09 8 module memory bus width 03 03 03 03 03 9 fine time base (ftb) dividend and divisor 52 52 52 52 52 10 medium time base (mtb) dividend 01 01 01 01 01 11 medium time base (mtb) divisor 08 08 08 08 08 12 minimum sdram cycle time ( t ck.min ) 14140f0f0f 13 reserved 00 00 00 00 00 14 cas latencies supported - lsb 06 04 1e 1c 14 15 cas latencies supported - msb 00 00 00 00 00 16 minimum cas latency time (t ck.min ) 64785a6978 17 minimum write recovery time (t wr.min ) 7878787878 18 minimum ras# tocas# delay time (t rcd.min ) 64785a6978 19 minimum row active to row active delay time (t rrd.min ) 50 50 3c 3c 3c 20 minimum row prechargetime (t rp.min ) 64785a6978 21 upper nibbles fo r t ras and t rc 11 11 11 11 11
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 38 11202007-pqti-i4uf 22 minimum active to precharge time (t ras.min ), lsb2c2c2c2c2c 23 minimum active to active/refresh time (t rc.min ), lsb90a48695a4 24 minimum refresh recovery time (t rfc.min ), lsbd0d0d0d0d0 25 minimum refresh recovery time (t rfc.min ), msb0202020202 26 minimum internal write to read command delay time (t wtr.min ) 3c 3c 3c 3c 3c 27 minimum internal read to precharge command delay time (t rtp.min ), msb 3c 3c 3c 3c 3c 28 upper nibble for t faw 01 01 01 01 01 29 minimum four activate window delay time (t faw.min )40402c2c2c 30 sdram output drivers supported 02 02 02 02 02 31sdram refresh options 8181818181 32 - 59 reserved 00 00 00 00 00 60 module nominal height 10 10 10 10 10 61 module maximum thickness 01 01 01 01 01 62 raw card used 01 01 01 01 01 63 address mapping from edge connector to dram 01 01 01 01 01 64 - 116 reserved 00 00 00 00 00 117 dimm manufacturer?s id code lsb 85 85 85 85 85 118 dimm manufacturer?s id code msb 51 51 51 51 51 119 module manufacturing location xx xx xx xx xx 120 - 121 module manufacturing date xx xx xx xx xx 122 - 125 module serial number xx xx xx xx xx 126 cyclical redundancy code lsb f6 f9 20 61 02 product type imsh1gu13a1f1c?08d imsh1gu13a1f1c?08e imsh1gu13a1f1c?10e imsh1gu13a1f1c?10f imsh1gu13a1f1c?10g organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 1 gbyte 64 64 64 64 64 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3? 6400u?5 pc3? 6400u?6 pc3? 8500u?6 pc3? 8500u?7 pc3? 8500u?8 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 39 11202007-pqti-i4uf 127 cyclical redundancy code msb c3 32 c2 6b 9e 128 product type, char 1 49 49 49 49 49 129 product type, char 2 4d 4d 4d 4d 4d 130 product type, char 3 53 53 53 53 53 131 product type, char 4 48 48 48 48 48 132 product type, char 5 31 31 31 31 31 133 product type, char 6 47 47 47 47 47 134 product type, char 7 55 55 55 55 55 135 product type, char 8 31 31 31 31 31 136 product type, char 9 33 33 33 33 33 137 product type, char 10 41 41 41 41 41 138 product type, char 11 31 31 31 31 31 139 product type, char 12 46 46 46 46 46 140 product type, char 13 31 31 31 31 31 141 product type, char 14 43 43 43 43 43 142 product type, char 15 2d 2d 2d 2d 2d 143 product type, char 16 30 30 31 31 31 144 product type, char 17 38 38 30 30 30 145 product type, char 18 44 45 45 46 47 146 module revision code, lsb 2x 2x 2x 2x 2x 147 module revision code, msb xx xx xx xx xx 148 dram manufacturer?s id code, lsb 85 85 85 85 85 149 dram manufacturer?s id code, msb 51 51 51 51 51 product type imsh1gu13a1f1c?08d imsh1gu13a1f1c?08e imsh1gu13a1f1c?10e imsh1gu13a1f1c?10f imsh1gu13a1f1c?10g organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 1 gbyte 64 64 64 64 64 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3? 6400u?5 pc3? 6400u?6 pc3? 8500u?6 pc3? 8500u?7 pc3? 8500u?8 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 40 11202007-pqti-i4uf 150 - 175 manufactures?s specific data 00 00 00 00 00 176 - 255 blank for customer use 0000000000 product type imsh1gu13a1f1c?08d imsh1gu13a1f1c?08e imsh1gu13a1f1c?10e imsh1gu13a1f1c?10f imsh1gu13a1f1c?10g organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 1 gbyte 64 64 64 64 64 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3? 6400u?5 pc3? 6400u?6 pc3? 8500u?6 pc3? 8500u?7 pc3? 8500u?8 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 41 11202007-pqti-i4uf table 22 spd codes for imsh1gu13a1f 1c?[13g/13h/13j/16h/16j] product type imsh1gu13a1f1c?13g imsh1gu13a1f1c?13h imsh1gu13a1f1c?13j imsh1gu13a1f1c?16h imsh1gu13a1f1c?16j organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 1 gbyte 64 64 64 64 64 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( x8) 2 ranks ( x8) label code pc3? 10600u? 8 pc3? 10600u? 9 pc3? 10600u? 11 pc3? 12800u? 9 pc3? 12800u? 11 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex 0 # of spd bytes utilized / # of bytes in spd / crc 92 92 92 92 92 1 spd revision 05 05 05 05 05 2 sdram technology key byte 0b 0b 0b 0b 0b 3 dimm module type 02 02 02 02 02 4 sdram density and banks 01 01 01 01 01 5 sdram addressing 09 09 09 09 09 6 module physical attributes 00 00 00 00 00 7 module organization 09 09 09 09 09 8 module memory bus width 03 03 03 03 03 9 fine time base (ftb) dividend and divisor 52 52 52 52 52 10 medium time base (mtb) dividend 01 01 01 01 01 11 medium time base (mtb) divisor 08 08 08 08 08 12 minimum sdram cycle time ( t ck.min ) 0c0c0c0a0a 13 reserved 00 00 00 00 00 14 cas latencies supported - lsb 36 3e 34 7e 7e 15 cas latencies supported - msb 00 00 00 00 00 16 minimum cas latency time (t ck.min ) 606c785a64 17 minimum write recovery time (t wr.min ) 7878787878 18 minimum ras# tocas# delay time (t rcd.min ) 606c785a64 19 minimum row active to row active delay time (t rrd.min ) 30 30 30 30 30 20 minimum row prechargetime (t rp.min ) 606c785a64
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 42 11202007-pqti-i4uf 21 upper nibbles fo r t ras and t rc 11 11 11 11 11 22 minimum active to precharge time (t ras.min ), lsb2020201818 23 minimum active to active/refresh time (t rc.min ), lsb808c98727c 24 minimum refresh recovery time (t rfc.min ), lsbd0d0d0d0d0 25 minimum refresh recovery time (t rfc.min ), msb0202020202 26 minimum internal write to read command delay time (t wtr.min ) 3c 3c 3c 3c 3c 27 minimum internal read to precharge command delay time (t rtp.min ), msb 3c 3c 3c 3c 3c 28 upper nibble for t faw 00 00 00 00 00 29 minimum four activate window delay time (t faw.min )f0f0f0f0f0 30 sdram output drivers supported 02 02 02 02 02 31sdram refresh options 8181818181 32 - 59 reserved 00 00 00 00 00 60 module nominal height 10 10 10 10 10 61 module maximum thickness 01 01 01 01 01 62 raw card used 01 01 01 01 01 63 address mapping from edge connector to dram 01 01 01 01 01 64 - 116 reserved 00 00 00 00 00 117 dimm manufacturer?s id code lsb 85 85 85 85 85 118 dimm manufacturer?s id code msb 51 51 51 51 51 119 module manufacturing location xx xx xx xx xx 120 - 121 module manufacturing date xx xx xx xx xx product type imsh1gu13a1f1c?13g imsh1gu13a1f1c?13h imsh1gu13a1f1c?13j imsh1gu13a1f1c?16h imsh1gu13a1f1c?16j organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 1 gbyte 64 64 64 64 64 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( x8) 2 ranks ( x8) label code pc3? 10600u? 8 pc3? 10600u? 9 pc3? 10600u? 11 pc3? 12800u? 9 pc3? 12800u? 11 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 43 11202007-pqti-i4uf 122 - 125 module serial number xx xx xx xx xx 126 cyclical redundancy code lsb 7c 05 51 a1 a0 127 cyclical redundancy code msb c7 67 db 13 1d 128 product type, char 1 49 49 49 49 49 129 product type, char 2 4d 4d 4d 4d 4d 130 product type, char 3 53 53 53 53 53 131 product type, char 4 48 48 48 48 48 132 product type, char 5 31 31 31 31 31 133 product type, char 6 47 47 47 47 47 134 product type, char 7 55 55 55 55 55 135 product type, char 8 31 31 31 31 31 136 product type, char 9 33 33 33 33 33 137 product type, char 10 41 41 41 41 41 138 product type, char 11 31 31 31 31 31 139 product type, char 12 46 46 46 46 46 140 product type, char 13 31 31 31 31 31 141 product type, char 14 43 43 43 43 43 142 product type, char 15 2d 2d 2d 2d 2d 143 product type, char 16 31 31 31 31 31 144 product type, char 17 33 33 33 36 36 145 product type, char 18 47 48 4a 48 4a 146 module revision code, lsb 1x 2x 2x 0x 0x 147 module revision code, msb xx xx xx xx xx product type imsh1gu13a1f1c?13g imsh1gu13a1f1c?13h imsh1gu13a1f1c?13j imsh1gu13a1f1c?16h imsh1gu13a1f1c?16j organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 1 gbyte 64 64 64 64 64 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( x8) 2 ranks ( x8) label code pc3? 10600u? 8 pc3? 10600u? 9 pc3? 10600u? 11 pc3? 12800u? 9 pc3? 12800u? 11 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 44 11202007-pqti-i4uf 148 dram manufacturer?s id code, lsb 85 85 85 85 85 149 dram manufacturer?s id code, msb 51 51 51 51 51 150 - 175 manufactures?s specific data 00 00 00 00 00 176 - 255 blank for customer use 0000000000 product type imsh1gu13a1f1c?13g imsh1gu13a1f1c?13h imsh1gu13a1f1c?13j imsh1gu13a1f1c?16h imsh1gu13a1f1c?16j organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 1 gbyte 64 64 64 64 64 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( x8) 2 ranks ( x8) label code pc3? 10600u? 8 pc3? 10600u? 9 pc3? 10600u? 11 pc3? 12800u? 9 pc3? 12800u? 11 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 45 11202007-pqti-i4uf table 23 spd codes for imsh1ge13a1f1c?[08d/08e/10e/10f/10g] product type imsh1ge13a1f1c?08d imsh1ge13a1f1c?08e imsh1ge13a1f1c?10e imsh1ge13a1f1c?10f imsh1ge13a1f1c?10g organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 1 gbyte 72 72 72 72 72 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3? 6400e?5 pc3? 6400e?6 pc3? 8500e?6 pc3? 8500e?7 pc3? 8500e?8 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex 0 # of spd bytes utilized / # of bytes in spd / crc 92 92 92 92 92 1 spd revision 05 05 05 05 05 2 sdram technology key byte 0b 0b 0b 0b 0b 3 dimm module type 02 02 02 02 02 4 sdram density and banks 01 01 01 01 01 5 sdram addressing 09 09 09 09 09 6 module physical attributes 00 00 00 00 00 7 module organization 09 09 09 09 09 8 module memory bus width 0b 0b 0b 0b 0b 9 fine time base (ftb) dividend and divisor 52 52 52 52 52 10 medium time base (mtb) dividend 01 01 01 01 01 11 medium time base (mtb) divisor 08 08 08 08 08 12 minimum sdram cycle time ( t ck.min ) 14140f0f0f 13 reserved 00 00 00 00 00 14 cas latencies supported - lsb 06 04 1e 1c 14 15 cas latencies supported - msb 00 00 00 00 00 16 minimum cas latency time (t ck.min ) 64785a6978 17 minimum write recovery time (t wr.min ) 7878787878 18 minimum ras# tocas# delay time (t rcd.min ) 64785a6978 19 minimum row active to row active delay time (t rrd.min ) 50 50 3c 3c 3c 20 minimum row prechargetime (t rp.min ) 64785a6978 21 upper nibbles fo r t ras and t rc 11 11 11 11 11
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 46 11202007-pqti-i4uf 22 minimum active to precharge time (t ras.min ), lsb2c2c2c2c2c 23 minimum active to active/refresh time (t rc.min ), lsb90a48695a4 24 minimum refresh recovery time (t rfc.min ), lsbd0d0d0d0d0 25 minimum refresh recovery time (t rfc.min ), msb0202020202 26 minimum internal write to read command delay time (t wtr.min ) 3c 3c 3c 3c 3c 27 minimum internal read to precharge command delay time (t rtp.min ), msb 3c 3c 3c 3c 3c 28 upper nibble for t faw 01 01 01 01 01 29 minimum four activate window delay time (t faw.min )40402c2c2c 30 sdram output drivers supported 02 02 02 02 02 31sdram refresh options 8181818181 32 - 59 reserved 00 00 00 00 00 60 module nominal height 10 10 10 10 10 61 module maximum thickness 01 01 01 01 01 62 raw card used 04 04 04 04 04 63 address mapping from edge connector to dram 01 01 01 01 01 64 - 116 reserved 00 00 00 00 00 117 dimm manufacturer?s id code lsb 85 85 85 85 85 118 dimm manufacturer?s id code msb 51 51 51 51 51 119 module manufacturing location xx xx xx xx xx 120 - 121 module manufacturing date xx xx xx xx xx 122 - 125 module serial number xx xx xx xx xx 126 cyclical redundancy code lsb 9c 93 4a 0b 68 product type imsh1ge13a1f1c?08d imsh1ge13a1f1c?08e imsh1ge13a1f1c?10e imsh1ge13a1f1c?10f imsh1ge13a1f1c?10g organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 1 gbyte 72 72 72 72 72 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3? 6400e?5 pc3? 6400e?6 pc3? 8500e?6 pc3? 8500e?7 pc3? 8500e?8 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 47 11202007-pqti-i4uf 127 cyclical redundancy code msb c2 33 c3 6a 9f 128 product type, char 1 49 49 49 49 49 129 product type, char 2 4d 4d 4d 4d 4d 130 product type, char 3 53 53 53 53 53 131 product type, char 4 48 48 48 48 48 132 product type, char 5 31 31 31 31 31 133 product type, char 6 47 47 47 47 47 134 product type, char 7 45 45 45 45 45 135 product type, char 8 31 31 31 31 31 136 product type, char 9 33 33 33 33 33 137 product type, char 10 41 41 41 41 41 138 product type, char 11 31 31 31 31 31 139 product type, char 12 46 46 46 46 46 140 product type, char 13 31 31 31 31 31 141 product type, char 14 43 43 43 43 43 142 product type, char 15 2d 2d 2d 2d 2d 143 product type, char 16 30 30 31 31 31 144 product type, char 17 38 38 30 30 30 145 product type, char 18 44 45 45 46 47 146 module revision code, lsb 2x 2x 2x 2x 2x 147 module revision code, msb xx xx xx xx xx 148 dram manufacturer?s id code, lsb 85 85 85 85 85 149 dram manufacturer?s id code, msb 51 51 51 51 51 product type imsh1ge13a1f1c?08d imsh1ge13a1f1c?08e imsh1ge13a1f1c?10e imsh1ge13a1f1c?10f imsh1ge13a1f1c?10g organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 1 gbyte 72 72 72 72 72 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3? 6400e?5 pc3? 6400e?6 pc3? 8500e?6 pc3? 8500e?7 pc3? 8500e?8 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 48 11202007-pqti-i4uf 150 - 175 manufactures?s specific data 00 00 00 00 00 176 - 255 blank for customer use 0000000000 product type imsh1ge13a1f1c?08d imsh1ge13a1f1c?08e imsh1ge13a1f1c?10e imsh1ge13a1f1c?10f imsh1ge13a1f1c?10g organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 1 gbyte 72 72 72 72 72 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3? 6400e?5 pc3? 6400e?6 pc3? 8500e?6 pc3? 8500e?7 pc3? 8500e?8 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 49 11202007-pqti-i4uf table 24 spd codes for imsh1ge13a1f 1c?[13g/13h/13j/16h/16j] product type imsh1ge13a1f1c?13g imsh1ge13a1f1c?13h imsh1ge13a1f1c?13j imsh1ge13a1f1c?16h imsh1ge13a1f1c?16j organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 1 gbyte 72 72 72 72 72 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( x8) 2 ranks ( x8) label code pc3? 10600e?8 pc3? 10600e?9 pc3? 10600e? 11 pc3? 12800e?9 pc3? 12800e? 11 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex 0 # of spd bytes utilized / # of bytes in spd / crc 92 92 92 92 92 1 spd revision 05 05 05 05 05 2 sdram technology key byte 0b 0b 0b 0b 0b 3 dimm module type 02 02 02 02 02 4 sdram density and banks 01 01 01 01 01 5 sdram addressing 09 09 09 09 09 6 module physical attributes 00 00 00 00 00 7 module organization 09 09 09 09 09 8 module memory bus width 0b 0b 0b 0b 0b 9 fine time base (ftb) dividend and divisor 52 52 52 52 52 10 medium time base (mtb) dividend 01 01 01 01 01 11 medium time base (mtb) divisor 08 08 08 08 08 12 minimum sdram cycle time ( t ck.min ) 0c0c0c0a0a 13 reserved 00 00 00 00 00 14 cas latencies supported - lsb 36 3e 34 7e 7e 15 cas latencies supported - msb 00 00 00 00 00 16 minimum cas latency time (t ck.min ) 606c785a64 17 minimum write recovery time (t wr.min ) 7878787878 18 minimum ras# tocas# delay time (t rcd.min ) 606c785a64 19 minimum row active to row active delay time (t rrd.min ) 30 30 30 30 30 20 minimum row prechargetime (t rp.min ) 606c785a64
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 50 11202007-pqti-i4uf 21 upper nibbles fo r t ras and t rc 11 11 11 11 11 22 minimum active to precharge time (t ras.min ), lsb2020201818 23 minimum active to active/refresh time (t rc.min ), lsb808c98727c 24 minimum refresh recovery time (t rfc.min ), lsbd0d0d0d0d0 25 minimum refresh recovery time (t rfc.min ), msb0202020202 26 minimum internal write to read command delay time (t wtr.min ) 3c 3c 3c 3c 3c 27 minimum internal read to precharge command delay time (t rtp.min ), msb 3c 3c 3c 3c 3c 28 upper nibble for t faw 00 00 00 00 00 29 minimum four activate window delay time (t faw.min )f0f0f0f0f0 30 sdram output drivers supported 02 02 02 02 02 31sdram refresh options 8181818181 32 - 59 reserved 00 00 00 00 00 60 module nominal height 10 10 10 10 10 61 module maximum thickness 01 01 01 01 01 62 raw card used 04 04 04 04 04 63 address mapping from edge connector to dram 01 01 01 01 01 64 - 116 reserved 00 00 00 00 00 117 dimm manufacturer?s id code lsb 85 85 85 85 85 118 dimm manufacturer?s id code msb 51 51 51 51 51 119 module manufacturing location xx xx xx xx xx 120 - 121 module manufacturing date xx xx xx xx xx product type imsh1ge13a1f1c?13g imsh1ge13a1f1c?13h imsh1ge13a1f1c?13j imsh1ge13a1f1c?16h imsh1ge13a1f1c?16j organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 1 gbyte 72 72 72 72 72 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( x8) 2 ranks ( x8) label code pc3? 10600e?8 pc3? 10600e?9 pc3? 10600e? 11 pc3? 12800e?9 pc3? 12800e? 11 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 51 11202007-pqti-i4uf 122 - 125 module serial number xx xx xx xx xx 126 cyclical redundancy code lsb 16 6f 3b cb ca 127 cyclical redundancy code msb c6 66 da 12 1c 128 product type, char 1 49 49 49 49 49 129 product type, char 2 4d 4d 4d 4d 4d 130 product type, char 3 53 53 53 53 53 131 product type, char 4 48 48 48 48 48 132 product type, char 5 31 31 31 31 31 133 product type, char 6 47 47 47 47 47 134 product type, char 7 45 45 45 45 45 135 product type, char 8 31 31 31 31 31 136 product type, char 9 33 33 33 33 33 137 product type, char 10 41 41 41 41 41 138 product type, char 11 31 31 31 31 31 139 product type, char 12 46 46 46 46 46 140 product type, char 13 31 31 31 31 31 141 product type, char 14 43 43 43 43 43 142 product type, char 15 2d 2d 2d 2d 2d 143 product type, char 16 31 31 31 31 31 144 product type, char 17 33 33 33 36 36 145 product type, char 18 47 48 4a 48 4a 146 module revision code, lsb 1x 2x 2x 0x 0x 147 module revision code, msb xx xx xx xx xx 148 dram manufacturer?s id code, lsb 85 85 85 85 85 product type imsh1ge13a1f1c?13g imsh1ge13a1f1c?13h imsh1ge13a1f1c?13j imsh1ge13a1f1c?16h imsh1ge13a1f1c?16j organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 1 gbyte 72 72 72 72 72 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( x8) 2 ranks ( x8) label code pc3? 10600e?8 pc3? 10600e?9 pc3? 10600e? 11 pc3? 12800e?9 pc3? 12800e? 11 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 52 11202007-pqti-i4uf 149 dram manufacturer?s id code, msb 51 51 51 51 51 150 - 175 manufactures?s specific data 00 00 00 00 00 176 - 255 blank for customer use 0000000000 product type imsh1ge13a1f1c?13g imsh1ge13a1f1c?13h imsh1ge13a1f1c?13j imsh1ge13a1f1c?16h imsh1ge13a1f1c?16j organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 1 gbyte 72 72 72 72 72 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( x8) 2 ranks ( x8) label code pc3? 10600e?8 pc3? 10600e?9 pc3? 10600e? 11 pc3? 12800e?9 pc3? 12800e? 11 jedec spd revision rev. 0.5 rev . 0.5 rev. 0.5 rev. 0.5 rev. 0.5 byte# description hex hex hex hex hex
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 53 11202007-pqti-i4uf 6 package outlines figure 2 package outline lg-dim-240-061 r/c a notes 1. sdram component outlines are symbolic representation of t he device placement. for act ual sdram outline details please refer to sdram component data sheet. "urr max allowed &0/?,' $)-???? -!8 ? ? ? -). $etail of contacts ? ? ? ? ? ? ? ? ? $rawing according to )3/ 'eneral tolerances ? $imensions in mm ? ?
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 54 11202007-pqti-i4uf figure 3 package outline lg-dim-240-062 r/c b notes 1. sdram component outlines are symbolic representation of t he device placement. for act ual sdram outline details please refer to sdram component data sheet. &0/?,' $)-???? -!8 ? ? ? -). $etail of contacts ? ? ? ? ? ? ? ? ? $rawing according to )3/ 'eneral tolerances ? $imensions in mm ? ?
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 55 11202007-pqti-i4uf figure 4 package outline lg-dim-240-064 r/c d notes 1. sdram component outlines are symbolic representation of t he device placement. for act ual sdram outline details please refer to sdram component data sheet. &0/?,' $)-???? -!8 ? ? ? -). $etail of contacts ? ? ? ? ? ? ? ? ? $rawing according to )3/ 'eneral tolerances ? $imensions in mm ? ?
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 56 11202007-pqti-i4uf figure 5 package outline lg-dim-240-065 r/c e notes 1. sdram component outlines are symbolic representation of t he device placement. for act ual sdram outline details please refer to sdram component data sheet. &0/?,' $)-???? ? ? ? ? ? ? ? ? -). $etail of contacts $rawing according to )3/ 'eneral tolerances ? $imensions in mm ? ? ? ? ? ?
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 57 11202007-pqti-i4uf 7 product type nomenclature for reference the applicable qimonda ddr3 dimm module nomenclature is listed in this chapter. table 25 example: ddr3 1gbyte unbuffered ecc module table 26 ddr3 dimm nomenclature field number 1234567891011121314 qimonda part number i m s h 1g e 1 3 a1 f1 c ? 08 e field description value coding 1 qimonda identifier i qi monda dimm modules 2 product group m module 3 power or application s standard llow power 4 product family h ddr3 5 density 51 512 mbytes 1g 1024 mbytes 6 module type / ecc support u 240 pin unbuffered dimms - non-ecc e 240 pin unbuffered dimms - ecc s 204 pin small outline dimms - non-ecc r 240 pin registered dimms - ecc p 240 pin registered dimms with parity bit - ecc 7 number of ranks 0 one rank of sdrams 1 two ranks of sdrams 2 four ranks of sdrams 8 dram device number of ios 2 4 components (2 2 ) 3 8 components (2 3 ) 4 16 components (2 4 ) 9 die revision a1 first 10 package f1 planar fbga, lead- and halogen-free f2 dual die fbga, lead- and halogen-free 9 temperature range c commercial (0 c - 95 c) 10 reserved for future use ? rfu 11 band width 08 pc3?6400, 6.4 gb/s, t ck = 2.5 ns, f ck =400 mhz 10 pc3?8500, 8.5 gb/s, t ck = 1.875 ns, f ck =533 mhz 13 pc3?10600, 10,66 gb/s, t ck = 1.5 ns, f ck =667 mhz 16 pc3?12800, 12,8 gb/s, t ck = 1.25 ns, f ck =800 mhz
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 58 11202007-pqti-i4uf 12 latencies d cl?rcd?rp = 5?5?5 e cl?rcd?rp = 6?6?6 f cl?rcd?rp = 7?7?7 g cl?rcd?rp = 8?8?8 h cl?rcd?rp = 9?9?9 j cl?rcd?rp = 10?10?10 field description value coding
imsh[51/1g][u/e]xxa1f1c ddr3 unbuffered dimm advance internet data sheet rev. 0.54, 2007-11 59 11202007-pqti-i4uf contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 speed bins and timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 speed bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 spd codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7 product type nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
edition 2007-11 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2007. all rights reserved. legal disclaimer the information given in this internet data sheet shall in no ev ent be regarded as a gua rantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hi nts given herein, any typical values stated herein and/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any kin d, including without limitation warranties of non-infringem ent of intellectual property rights of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. qimonda components may only be used in life-support devices or systems with the express writte n approval of qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support devi ce or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the he alth of the user or other persons may be endangered. www.qimonda.com advance internet data sheet

▲Up To Search▲

Price & Availability of IMSH1GU13A1F1C-10F

	To Download IMSH1GU13A1F1C-10F Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .